A planar device, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), has its source, gate and drain arranged in a direction substantially parallel to a substrate surface. Due to such an arrangement, it is difficult for the planar device to have its footprint further scaled down or its manufacture cost further reduced. In contrast, a vertical device has its source, gate and drain arranged in a direction substantially perpendicular to the substrate surface. Therefore, it is relatively easier for the vertical device to be scaled down or reduced in manufacture cost, as compared to the planar device. Nanowire based Vertical Gate-all-around Field Effect Transistor (V-GAAFET) is a candidate for future high-performance devices.
However, for the V-GAAFET, it is difficult to control its gate length, especially for those with a single-crystalline channel material. This is because conventionally the gate length depends on timing etching, which is difficult to control. On the other hand, it is a great challenge in the Integrated Circuit (IC) industry to make an IC unit including stacked V-GAAFETs (especially those having different conductivity types) with high performances and small footprint.